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1/11 february 2005 STP40N20 stw40n20 n-channel 200v - 0.038 ? - 40a to-220/to-247 low gate charge stripfet? mosfet table 1: general features typical r ds (on) = 0.038 ? gate charge minimized very low intrinsic capacitances very good manufacturing repeatibility excellent figure of merit (r ds *q g ) 100% avalanche tested description this mosfet series realized with stmicroelec- tronics unique stripfet process has specifically been designed to minimize input capacitance and gate charge. it is therefore suitable as primary switch in advanced high-efficiency isolated dc-dc converters. applications high current, high speed switching ups table 2: order codes figure 1: package figure 2: internal schematic diagram type v dss r ds(on) i d pw STP40N20 stw40n20 200 v 200 v < 0.045 ? < 0.045 ? 40 a 40 a 160 w 160 w 1 2 3 1 2 3 to-220 to-247 sales type marking package packaging STP40N20 p40n20 to-220 tube stw40n20 w40n20 to-247 tube rev. 2
STP40N20 - stw40n20 2/11 table 3: absolute maximum ratings ( ) pulse width limited by safe operating area (1) i sd 40a, di/dt 200 a/s, v dd v (br)dss , t j t jmax. table 4: thermal data table 5: avalanche characteristics symbol parameter value unit v ds drain-source voltage (v gs = 0) 200 v v dgr drain-gate voltage (r gs = 20 k ? ) 200 v v gs gate- source voltage 20 v i d drain current (continuous) at t c = 25 c40a i d drain current (continuous) at t c = 100 c25a i dm ( ) drain current (pulsed) 160 a p tot total dissipation at t c = 25 c 160 w derating factor 1.28 w/ c dv/dt (1) peak diode recovery voltage slope 12 v/ns t j t stg operating junction temperature storage temperature -55 to 150 c to-220 to-247 rthj-case thermal resistance junction-case max 0.78 c/w rthj-amb thermal resistance junction-ambient max 62.5 50 c/w t l maximum lead temperature for soldering purpose 300 c symbol parameter max value unit i ar avalanche current, repetitive or not-repetitive (pulse width limited by t j max) 40 a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar , v dd = 50 v) 230 mj
3/11 STP40N20 - stw40n20 electrical characteristics (t case =25 c unless otherwise specified) table 6: on/off table 7: dynamic table 8: source drain diode (1) pulsed: pulse duration = 300 s, duty cycle 1.5 %. (2) pulse width limited by safe operating area. symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 1ma, v gs = 0 200 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating v ds = max rating, t c = 125 c 1 10 a a i gss gate-body leakage current (v ds = 0) v gs = 20v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 2 3 4 v r ds(on) static drain-source on resistance v gs = 10v, i d = 20 a 0.038 0.045 ? symbol parameter test conditions min. typ. max. unit g fs (1) forward transconductance v ds = 15 v , i d =20 a 30 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds = 25v, f = 1 mhz, v gs = 0 2500 510 78 pf pf pf t d(on) t r t d(off) t r turn-on delay time rise time turn-off delay time fall time v dd = 100 v, i d = 20 a, r g = 4.7 ? v gs = 10 v (resistive load see, figure 17) 20 44 74 22 ns ns ns ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd = 160v, i d = 40 a, v gs = 10v 75 13.2 35.5 nc nc nc symbol parameter test conditions min. typ. max. unit i sd i sdm (2) source-drain current source-drain current (pulsed) 40 160 a a v sd (1) forward on voltage i sd = 20 a, v gs = 0 1.5 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 20 a, di/dt = 100a/s v dd = 100v, t j = 25 c (see test circuit, figure 18) 192 922 9.6 ns nc a t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 20 a, di/dt = 100a/s v dd = 100v, t j = 150 c (see test circuit, figure 18) 242 1440 11.9 ns nc a
STP40N20 - stw40n20 4/11 figure 3: safe operating area for to-220 figure 4: safe operating area for to-247 figure 5: output characteristics figure 6: thermal impedance for to-220 figure 7: thermal impedance for to-247 figure 8: transfer characteristics
5/11 STP40N20 - stw40n20 figure 9: transconductance figure 10: gate charge vs gate-source voltage figure 11: normalized gate threshold voltage vs temperature figure 12: static drain-source on resistance figure 13: capacitance variations figure 14: normalized on resistance vs tem- perature
STP40N20 - stw40n20 6/11 figure 15: source-drain forward characteris- tics
7/11 STP40N20 - stw40n20 figure 16: unclamped inductive load test cir- cuit figure 17: switching times test circuit for resistive load figure 18: test circuit for inductive load switching and diode recovery times figure 19: unclamped inductive wafeform figure 20: gate charge test circuit
STP40N20 - stw40n20 8/11 dim. mm. inch min. typ max. min. typ. max. a 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 d 15.25 15.75 0.60 0.620 e 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 f 1.23 1.32 0.048 0.052 h1 6.20 6.60 0.244 0.256 j1 2.40 2.72 0.094 0.107 l 13 14 0.511 0.551 l1 3.50 3.93 0.137 0.154 l20 16.40 0.645 l30 28.90 1.137 ? p 3.75 3.85 0.147 0.151 q 2.65 2.95 0.104 0.116 to-220 mechanical data
9/11 STP40N20 - stw40n20 dim. mm. inch min. typ max. min. typ. max. a 4.85 5.15 0.19 0.20 a1 2.20 2.60 0.086 0.102 b 1.0 1.40 0.039 0.055 b1 2.0 2.40 0.079 0.094 b2 3.0 3.40 0.118 0.134 c 0.40 0.80 0.015 0.03 d 19.85 20.15 0.781 0.793 e 15.45 15.75 0.608 0.620 e5.45 0.214 l 14.20 14.80 0.560 0.582 l1 3.70 4.30 0.14 0.17 l2 18.50 0.728 ? p 3.55 3.65 0.140 0.143 ? r 4.50 5.50 0.177 0.216 s5.50 0.216 to-247 mechanical data
STP40N20 - stw40n20 10/11 table 9: revision history date revision description of changes 27-sep-2004 1 first release. 03-feb-2005 2 complete version
11/11 STP40N20 - stw40n20 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america

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